1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly relates to a semiconductor device which is provided with a test-mode function to test operations of the semiconductor device.
2. Description of the Related Art
Semiconductor memory devices such as DRAMs are usually designed such that a data-output configuration (an output-interface configuration) thereof can be chosen from a 4-bit configuration, an 8-bit configuration, and a 16-bit configuration if a total of 16 data-output nodes are provided, for example. A selection and setting of a desired configuration can be made at the time of shipment from a factory by operating fuse wires.
When a 4-bit configuration is selected, for example, data is output only from 4 predetermined data-output nodes, and 12 remaining data-output nodes do not output data. In this case, one column-address access results in an output of 4-bit data. If an 8-bit configuration is selected, 8 predetermined data-output nodes are used for data output, and 4 other data-output nodes are not used. That is, 8-bit data is obtained when making a column-address access. In the case of a 16b-bit configuration, all of the 16 data-output nodes are used for data output, thereby providing 16-bit data upon a column-address access.
When a 64-Mega-bit semiconductor memory device is taken as an example, a selection of a 4-bit output configuration results in the number of possible consecutive accesses being 16 Mega in a direction of column addresses. That is, one data-output node can output 16-Mega bits of data consecutively. In the case of a 16-bit output configuration, the number of consecutively accessible data is 4 Mega in the column direction, so that one data-output node can output 4-Mega bits of data consecutively.
FIG. 1 is a circuit diagram showing a configuration of related-art data-bus switches which implement an output configuration as described above. In FIG. 1, the data-bus switches are shown only with respect to four data-output nodes DQ0 to DQ3 for the sake of explanation.
In FIG. 1, four data nodes DQ0 through DQ3 are provided to output data from a data buffer 600. For each piece of data which is output from a respective one of the data nodes DQ0 through DQ3, a corresponding one of data-bus switches 500-0 through 500-3 is provided. Namely, data supplied from the data-bus switch 500-1, for example, is output from the data node DQ1 via the data buffer 600.
The data-bus switch 500-0 includes inverters 501 through 504, data-transfer gates 505 through 507, and a NOR circuit 508. The data-bus switch 500-1 includes inverters 511 through 513, a data-transfer gate 514, and a NOR circuit 515. The data-bus switch 500-2 includes inverters 521 through 525 and data-transfer gates 526 through 530. The data-bus switch 500-3 includes inverters 531 through 533, a data-transfer gate 534, and a NOR circuit 535. Each transfer gate is comprised of a PMOS transistor and an NMOS transistor which are connected in parallel.
In the configuration of FIG. 1, all of the data nodes DQ0 through DQ3 are used for data-output purposes when a 16-bit-output configuration is selected (the same bus-switch configuration as that for DQ0 through DQ3 is provided for each of DQ4-DQ7, DQ8-DQ11, and DQ12-DQ15). In this case, the data nodes DQ0 through DQ3 output data dat00, dat11, dat22, and dat33, respectively.
In the case of an 8-bit-output configuration, only DQ0 and DQ2 are used among the data nodes DQ0 through DQ3 for the purpose of data output. The data nodes DQ0 and DQ2 in this case output data dat00 and dat22, respectively.
When a 4-bit configuration is selected, only DQ2 among the data nodes DQ0 through DQ3 is used for outputting data. The output data is data dat20 in this case.
Data datmn (m=1, 2, 3; n=1, 2, 3) represents an n-th bit of the parallel data supplied from memory cells with respect to a data node DQm. Data selection as to which bit is selected from the parallel data is made by signals gatemn (m=1, 2, 3; n=1, 2, 3). When a particular signal gatemn is HIGH, a corresponding data-transfer gate is opened, so that selected data is output from the data node DQm via a data bus DB and the data buffer 600.
Selection of an output configuration is made by selection signals dx4z and dx16z. When the selection signal dx4z is HIGH, the 4-bit-output configuration is chosen. When the selection signal dx16z is HIGH, the 16-bit-output configuration is selected. In other cases, the 8-bit-output configuration is selected.
In this manner, data is output from the data nodes DQ0 through DQ3 (in reality, from the data nodes DQ0 through DQ15).
Semiconductor devices, in general, are provided with a test-mode function to conduct a test on operations thereof, and test results are output from the data nodes DQ.
As described above, the data-output configuration is selected from and fixed to one of the 16-bit configuration, 8-bit configuration, and 4-bit configuration. Because of this, data nodes used for outputting test results should be the four data nodes which are used in the 4-bit configuration. If the data node DQ0, for example, is used for the purpose of outputting a test result in FIG. 1, the 16-bit configuration and the 8-bit configuration can send the test result to an exterior of the device without a problem, but the 4-bit configuration will fail to output the test result. That is, if the 4-bit configuration is selected and fixed, then, no access can be made to the test result form the exterior of the device. The configuration of FIG. 1, therefore, is such that a test result TSRST is output from the data node DQ2 via the data-bus switch 500-2.
During a test mode, a test-mode-indication signal testz is HIGH. This suspends data output from the data nodes DQ0, DQ1, and DQ3, which are not used during the test operation. Also, data as normally output from the data node DQ2 is suspended, and the test result TSRST is instead sent out via the data node DQ2. Suspension of unnecessary data output makes it possible to suppress electric-current consumption.
The configuration as described above normally allows a test to be properly conducted and a test result to be properly obtained. When the test result is susceptible to power-voltage noise caused by a fluctuation in an electric-current consumption inside the semiconductor device, for example, the above-described configuration may fail. Where the 16-bit-output configuration is selected and fixed, for example, the data bus DB is driven with respect to all the 16 bits of data during normal operations. Current consumption in this case is much larger than that of the 4-bit-output configuration. In the configuration of FIG. 1, the data bus DB is driven only with respect to 4 bits of data during the test operation since only 4 bits of data are output in the test mode. This means that current-consumption conditions as observed in the 16-bit-output configuration cannot be tested during the test mode.
DLL (delay-locked loop) circuits, provided for the purpose of timing adjustments of synchronization signals, are sensitive to a power-voltage fluctuation caused when current consumption fluctuates, so that such configuration as shown in FIG. 1 cannot allow a test on the DLL circuits to be properly conducted.
Accordingly, there is a need for a semiconductor device which can properly conduct a test on operations thereof under such current-consumption conditions as would be observed when additional data buses are driven in excess of a particular data bus necessary to be driven for outputting a test result.